5h ago
Huawei's Ascend roadmap delays 3D LogicFolding until 2030, leaving upcoming 910C and 950 chips reliant on 2.5D packaging
The roadmap plans 30-kilowatt wafer-scale processors by 2031
The roadmap plans 30-kilowatt wafer-scale processors by 2031
@teortaxesTex W2W HB is easier than D2D or D2W
WSE-2 consumes 20kW while WSE-3 consumes 23kW
ok what the hell. I missed this completely So, Huawei expects to deploy LogicFolding Ascends in 2030/31, and have >400 Mtr/mm^2, *and* have single-chip power draw of 30KW. I think this must mean heavy design for yield and, likely, Cerebras-style wafer-scale engines.
What's the largest WSE-3-based cluster? I see there were plans for max 2048 "systems" (ie wafers). That's 47 MW, plus change. Huawei 950 SuperCluster is likely >500 MW, 960 (2027) >1 GW? And they want >30 KW *chips* by 2030. Imagine. 32K wafers, working as one.
WSE-2 consumes 20kW while WSE-3 consumes 23kW