What is Digg?24 Comments
- Kanna, on 10/12/2007, -1/+19OP: You're doing it wrong.
http://www.digit-life.com/articles2/editorial/amd-guiseppe-amato-conf-part1.html - sleepyness, on 10/12/2007, -3/+14K8L seems pretty good. AMD seems to employ so much more innovation than Intel. Plus the fact that their quad core is native instead of 2 Core 2 Duos glued together.
- macbookpromat, on 10/12/2007, -3/+11Well I have to say that AMD may come out on top in the multi-core processor industry. Not because it's processors are faster, but because they are innovative. Sure Intel might be ahead right now, but their plan for 4x core processors is rediculous.
On another note, why are GPU's becoming more power consuming by the second while the CPU market is based on lowest power consumption possible to acheive maximum performance (correct me if I'm wrong but this is just a misinformed opinion). Shouldn't N'Vidia and ATI learn from the CPU market to make less energy-sucking GPU's? - MikeCerm, on 10/12/2007, -1/+9Granted, Pentium D was just 2 shoddy chips glued together, but Pentium D wasn't the mistake, Netburst was. Pentium D chips weren't any worse than the P4 chips that they were based on. AMD's design was just better, both single and dual-core.
- CoolGoose, on 10/12/2007, -4/+11Imho Intel is doing the same Pentium D mistake again
- duke_nate, on 10/12/2007, -1/+7Great article once you actually find it.
- combatchuck, on 10/12/2007, -0/+6I disagree that dual processors is equal to dual core. First, the processors in a DP system talk over the system bus, which is way slower than if they talk over a direct connection. Not just because of the lower clock speed of the external bus, but because of the length of the wires. I would imagine that, with the speed of today's processors and how much latency can kill their performance, 3 inches of wire between the 2 processors is a (relatively) very, very long way.
- jdavid, on 10/12/2007, -0/+6amd's purchase of ATI is about leveraging x8664 and creating a x8664 AsMP(Asymetrical Multi-Processing) the idea is to increase core count beyond 30 cores, kinda like system on a chip. Imagine what would happen to computing, if the pci bus/pci-express buss were replaced and integrated into hypertransport.
imagine if you bought a single chip with 4 x8664 cores, 2 application cores, 30 graphics cores(they call them pipelines), an AI core, and a small FPGA to upgrade some of the logic between cores, instead of running software like a bios to fix bugs, you would actually fix hardware bugs in hardware.
The future of CPU, is more aysymetric than symetric, x86 design does not map towards the future use of software, it maps to functional programing design patterns, where multiprocessing maps better towards objects that run on threads.
in a simulated world, streaming processors, like graphics cards, handle data better. remember when MMX came out. (Multi-Media Extentions) MMX was just the start of including small optimized pipelines for graphics and world simulation calculations. when you simulate a world, you get very specific on calculating something like a box or a triangle, an object, a physical object; you then determine how many of those you want to model per frame, frames per second, you then know how many calculations you need. You can either do them, 1 pipe per object, or many objects per pipe. right now the calculations are simple enough that simulating many objects per pipe makes sense. so they are time divided, and each object gets maybe 1-2thousand opperations, before the next one calculates. the logic and the math are straightforward and highly repeated, so the design can be fairly formal with a limited amount of branch prediction.
user interfaces on the other hand, create computational complexity, because you need to predict and react to the user's commands. x86 is far better at doing this. one version of the x86 design allowed for 64,000 different opperational commands, to better deal with varries ways to save an op because a user might do something unique. Risc tried to do this, but its slow and straight forward way of dealing with branching like graphics cards are limited made code for applications like MS Word, very slow, an code for SQL trasactions fast.
I cant wait for AMD to replace x86 through attrittion. - MikeCerm, on 10/12/2007, -2/+7Core 2 Duo is the worst name ever, and I think that Intel chose their new numbering scheme specifically to confuse consumers.
The problem all started when they decided to rename the Pentium M the "Core". If they weren't changing the chips, they should have made that the last of the Pentium line, saved the "Core" moniker for Conroe.
We know that Core 2 Quadro is after Core 2 Duo, but what's next? Core 3 Octo? - inactive, on 10/12/2007, -0/+5CPUs are extensively used in server applications. Graphic cards are not.
In a server enviroment you'll have several racks of computers with multiple processors. That gets very hot and uses a lot of power.
If you're using a GPU - you've probably got one computer sitting on your desk and heat isn't really as much of an issue. - lostmongoose, on 10/12/2007, -1/+5@gemini: two dies connected with a crossbar is not the same as native quad core. So, no Intel will not physically have CPUs with quad core dies first, because rather than actually work on getting native quad core, they're more worried about beating AMD to the punch, so they release a another multi-die chip and label it quad core and no one in the consumer world realizes this isn't what they're really getting and, as long as the software treats it as such, no one bothers calling shenanigans on them.
- MikeCerm, on 10/12/2007, -0/+3I think that companies like Google and every visual-effects company in Hollywood have done pretty well with clustering x86 hardware. The server sprawl problem with is getting better and better with dual-core, and now quad, and the Sun and Cray supercomputer folks really just can't compete with x86 from a price-performance standpoint.
Clustering is a pain in the ass for you and me, but people that actually need clusters find ways to make it work. - Kazbaeden, on 10/12/2007, -1/+4Yeah, I was just gonna say there's less than a paragraph about the K8L in the linked article. I don't think the OP even read his link.
- hurfydurfur, on 10/12/2007, -0/+2Yeah, good article. Very internal oriented especially with the last bits about placing the product with the customer application. They talk about server sprawl which is really funny considering that's the strength of the x86 platform versus the vertical scaling of Sun (100+ cpus in one box). x86 is cheaper but doesn't have a way to scale massively in the vertical direction, however the performance per price is ridiculous.
So when they mention "clustering", I shudder because that's the downside. Clustering isn't some magical button. Look at Beowulf's lack of usability for anything that's an off-the-shelf product. Look at the job scheduling design of Oracle's "grid". Look at the complexity/price and rebranded SunCluster. Look at Blizzard's own sharding (which has managability problems and complexity ... speculating based on downtime ... I have no source for this). It's not really that great. But then you have vmware (I'm no expert in this) which claims you can move running apps between hardware with their ESX server thing. Running apps! Clearly this is the way to do it, not clustering. Virtualization. If I had done these slides, I would have said "centralized" not "clustered". Clustering is a cluster-fork, imho. I think vmware has a better product, although many people have compained about "virtual server sprawl", so maybe it doesn't solve anything. - HappyScrappy, on 10/12/2007, -1/+3The power slide makes no sense.
Running cores at lower frequencies only saves power (versus run and halt) if you also run them at lower voltages.
Running different cores at different voltages requires CPU power supply changes, as current CPU power supplies are only designed to output one voltage at a time. This voltage can be adjusted up and down, but you can't generate two at once.
If you cannot adjust voltage separately, then just running all at the same speed and then halting them when they don't have work to do uses no more power than running at the lower frequency. And if you run them at full speed and not only halt them but power them down when they are not busy, you actually save power versus running them slower due to reduced leakage currents.
I can't see how AMD's power page makes any sense here. Does someone have more details that make this description make sense?
As to the lower graph, it cites this URL:
http://techreport.com/etc/2006q2/woodcrest/index.x?pg=2
The URL shows the top Dempsey chip at 130W. It shows the top Woodcrest at 80W.
Yet the AMD slide shows Dempsey at 260W and Woodcrest at 130W.
Where does AMD get these bogus numbers from?
The slide shows the top Clovertown at 160W, which is likely given that Clovertown is basically two Woodcrests.
If you change these bars to what is on the referenced page, Dempsey comes in at just a hair over the Opteron DDR2 on the left. And the Woodcrest comes in a lot lower than the Opteron DDR2 on the left.
I also wonder how the memory power usage of Clovertown is expected to be the same as Dempsey if the memory clock is scaled back 20% (as mentioned on the page).
Finally, the 83W number is just too high for most systems. 83W probably would be correct for FB-DIMMs, but few people use FB-DIMMs.
It'll also be funny to see this graph in a year when AMD has 65nm on the left and on the right, and their state TDP is estimated to rise by ~23% to 50%, while Intel falls to 45nm and their TDP is flat. - geminitojanus, on 10/12/2007, -3/+5Well you are misinformed, but only by the former part in your statement; AMD's not being innovative in this case, they're just committed to native quad core, simply because they have to be. Intel's simply looking for a way to use the volumes and volumes of cores it's making in a better fashion. And what's a better way to use excess supply than to simply stick two of them together and sell them for a bit more?
AMD's "native quad core initiative" doesn't take much more thinking than Intel's own quad core initiative, especially as AMDs is simpler to implement all on one chip (thanks to HyperTransport). Intel's basically pulling magic out of their asses to make two, dual core chips work on the same platform as a single quad core chip, without changing sockets, especially with an old, braindead interconnect technology like FSB.
Also note that they're marketing the HELL out of this chip, even though it's going to be 6 months before anyone sees it (and more like 9 before it ships). Intel shut their mouth and handed their chips over to people to play with prior to Conroe/Woodcrest, and the marketing blitz attack came on launch, /after/ the fact where everyone knew these chips would blow the marketplace apart. The whole "Conroe being the not-so-secret weapon" comment of prior articles sums up exactly what happened, and why AMD is reeling to catch up.
As for this part: "why are GPU's becoming more power consuming by the second while the CPU market is based on lowest power consumption possible to acheive maximum performance (correct me if I'm wrong but this is just a misinformed opinion). Shouldn't N'Vidia and ATI learn from the CPU market to make less energy-sucking GPU's?"
Graphics card companies don't give a damned about power consumption because their market doesn't care about power consumption. They market chips to gamers who want MORE POWER, and aren't bothered with //KILOWATT// power usages. The same technology that works for Intel and AMD for saving power would work great on graphics cards, even more so considering you could turn off entire pipelines for times you didn't need the capacity, they're just not interested. Where it's going to end up biting them in the ass however, is when they start hitting the thermal wall where even the most elitist overclockers on the planet won't touch their hardware because it pumps out more heat than the sun. Who knows where this point will actually be, however, as the companies are already quite happy with thermoelectric cooling and heatpipes.
I suspect that once the mobile market for graphics power picks up, that the companies will renew interest in low power alternatives, and that the technology will trickle back to their mainstream counterparts. However, until then, don't expect much. - inactive, on 10/12/2007, -1/+3Intel's naming scheme is really confusing for most people. The Core2 lineup make a little more sense than the names they used with the pentiums, but just not by much.
At least with AMD you knew that the higher number meant better performance.
Intel just neede a way to sneakily back out of the horendous crap that was netburst running at twice the clockrate of AMD chips that were faster. - inactive, on 10/12/2007, -2/+3Well, most GPUs dynamically scale their memory and CPU clocks. Ever notice how your card has two sets of speeds on it? The low speed is for 'easy lifting' 2d, the high speed (and the high speed fan that accompanies it) is for 3d. So power management isn't really an issue for these cards most of the time. If you're not gaming 24/7 on an SLi rig, you should be doing just fine.
- aeiou, on 10/12/2007, -2/+3is intel's really any better?
- geminitojanus, on 10/12/2007, -2/+3"Amd's purchase of ATI is about leveraging x8664 and creating a x8664 AsMP(Asymetrical Multi-Processing) the idea is to increase core count beyond 30 cores, kinda like system on a chip. Imagine what would happen to computing, if the pci bus/pci-express buss were replaced and integrated into hypertransport."
Computers are moving more towards SoIC (whatever you want to call the next step past "Very Wide Scale Integration"), and buying ATi will help in the extreme long run with this, but in the present and the nearer future, the PCI/Express bus could already be ditched for HyperTransport... that is, if anyone actually made anything other than processors that talked using the HyperTransport lingo, and HyperTransport defined a riser-card connector. But the real problem here is that AMD would have a really, really hard time getting companies to start making more HyperTransport compatible chips, especially as PCI Express is already being implemented by a great deal of companies, and offers a simpler upgrade path for existing IP.
What I'm saying is this: anything AMD wants to integrate onto their own chips is going to have to talk HyperTransport, and this alone is the reason for purchasing ATi now (as CPU-GPU interaction will be the biggest selling point for consoles and for home gamers in the 2008-10 generation). Getting the graphic coress to talk HyperTransport might not be such an easy feat, but it will probably be a great way for AMD to force the hand of other players and get HyperTransport on other controllers.
However, x86 going the way of the dinosaur is going to take both Intel and AMD moving away from x86, and neither player is very fixated on this concept (though Intel _refuses_ to give up on Itanium, which might end up being their way of switching as the compilers for this hardware gets better, and the hardware becomes cheaper to manufacture). Most of the concept of having multiple, specific cores already exists today (we have Integer "cores", Floating point "cores", Vector "cores" and Load/Store "cores" on a chip now, we just don't think of them as this anymore, as it's been years since these were actually integrated into our hardware), with the main problem being "how do we use all of this stuff at the same time?"
Most of the stuff you go ranting onto will require an altogether different revolution, one to VLIW, which in effect is a step Intel's already made with their massively parallel Itanium chip (and their EPIC; explicitly parallel instruction computing, very long instruction word by another name). - hhcv, on 10/12/2007, -4/+4One improvement would me a naming scheme that made sense!
- Janus67, on 10/12/2007, -2/+0Well maybe in a generation or two (remember AMD bought ATI a month or so ago). It is still a different technology (similar but different) and they do different things. The processes are also different sizes.
- geminitojanus, on 10/12/2007, -8/+5Too bad Intel will have quad core first, and will likely maintain the performance lead this way, especially with Intel being so close to 45nm going live (two 45nm chips side-by-side would greatly cut power, depending on die-size it could quite possibly be smaller than a single quad-core at 65nm). AMD's native quad core technology seems to be something they're really trying to sell now, which is interesting considering that it's still at least 9 months away and Intel's kept relatively tight lipped about Clovertown/Kentsfield, and even more quiet about Tigerton and processors ahead of it.
It's also funny AMD seems to think Intel's not launching Clovertown with a 1333MHz bus option, even though they've stated in their marketing literature they were going to release Clovertowns with a 1066MHz FSB with the speedgrade number ending in -0, and those with 1333MHz ending with -5. (http://www.dailytech.com/article.aspx?newsid=4253 )
Any way around, cudos to AMD for finally making it to 65nm (shipping in December instead of Q107), and for taking the initiative to add a L3 cache, more coarse grained power enhancements, and other improvements (that they aren't talking about, but which are very similar to those in Conroe) to K8L, coming to us sometime Q207. - inactive, on 10/12/2007, -7/+2Dual core, quad core only flannel. If you have an old dual processor SMP machine thats equal with a dualcore. Nothing new here, only marketing. And I agree with that assumption x86 doesn't have a way to scale massively.
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