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One concept that makes this practical is LogicFolding.
Traditional chips spread logic across a flat surface.
LogicFolding brings related logic closer together by moving toward more 3D structures.
Less distance means less delay.
And in AI workloads, small delays compound fast.
For decades, the industry had a clear playbook:
→ Shrink transistors → Increase density → Improve performance → Lower cost
Moore’s Law powered the modern computing era.
But that curve is slowing.
The next optimization target is not only geometry.
It is latency.
This is the idea behind Tau Scaling Law, also known among peers as Her’s Law.
Instead of asking only, “How small can the chip get?”
We now have to ask:
→ Where is time being lost? → Where is data waiting? → Where are signals traveling too far? → Where is the system creating friction?
The enterprise takeaway is simple:
AI performance is now a system-level challenge.
The winners will optimize chips, memory, interconnects, software, and architecture together.
Less latency means faster intelligence. Less movement means lower cost. Less waste means AI that can scale.
Read the full Article https://www.linkedin.com/pulse/ais-next-leap-time-ronald-van-loon-ic7te
Where do you think the biggest AI infrastructure gains will come from next, smaller chips, better systems, or something else entirely?
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