Imec scales superconducting interconnects to 30 nm, eeNews Europe reports
eeNews Europe says the technology uses 300 mm CMOS-compatible processes and targets future high-performance computing and AI accelerators.
eeNews Europe says the technology uses 300 mm CMOS-compatible processes and targets future high-performance computing and AI accelerators.
Imec has scaled NbTiN superconducting interconnects—the wiring between circuit components—to a 30 nm linewidth, around ten times smaller than conventional niobium technology, eeNews Europe reports. The publisher says Imec also demonstrated circuits with a density of 3.8 million Josephson junctions per cm². Beyond future high-performance computing and AI accelerators, eeNews Europe describes potential applications in quantum systems, neuromorphic computing and photon detection.
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eeNews Europe says the technology uses 300 mm CMOS-compatible processes and targets future high-performance computing and AI accelerators.
Imec has scaled NbTiN superconducting interconnects—the wiring between circuit components—to a 30 nm linewidth, around ten times smaller than conventional niobium technology, eeNews Europe reports. The publisher says Imec also demonstrated circuits with a density of 3.8 million Josephson junctions per cm². Beyond future high-performance computing and AI accelerators, eeNews Europe describes potential applications in quantum systems, neuromorphic computing and photon detection.
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