3D DRAM will unlock a whole new dimension (literally) in computer architecture.

It'll be presented at ISCA 2026 later this month.

3 things you should know: 1. Stacking DRAM on compute, allows us to co-design them together just like how it is done with SRAM now. 2. The power numbers are very good 0.3-0.4 pJ/bit (compared to HBM's 3-4 pJ/bit). 3. 3D dram allows you to pull 100K+ lanes into the compute die, unlike 2K lanes in HBM4. Imagine the speed.

I co-authored this paper. It'll be part of the conference proceedings, but I'll write an article on http://chiplog.io shortly after.