Future Huawei Ascend chips target up to 8 PFLOPS.
@zephyr_z9 I kind of forgot Rubin is that OP in fp4 how did they even do this?
The gap is much larger on a FLOP basis Ascend is 2PFLOPS on fp4 while Rubin is 50PFLOPS FLOPS/W is 21 TFLOPS/W for Rubin, while it is less than 3 TFLOPS/W for Ascend 950DT
@teortaxesTex Nothing tbh They will probably change it
@zephyr_z9 What stops Huawei from doing this? Even 970 is scheduled to have the old 1/x relationship between perf and precision.
@zephyr_z9 What stops Huawei from doing this? Even 970 is scheduled to have the old 1/x relationship between perf and precision.
@teortaxesTex By gutting the fp32/fp64 ALUs and pumping up the numbers for fp4 ALUs
Future Huawei Ascend chips target up to 8 PFLOPS.
@zephyr_z9 I kind of forgot Rubin is that OP in fp4 how did they even do this?
The gap is much larger on a FLOP basis Ascend is 2PFLOPS on fp4 while Rubin is 50PFLOPS FLOPS/W is 21 TFLOPS/W for Rubin, while it is less than 3 TFLOPS/W for Ascend 950DT