AMD says the processors are designed to work within data centers’ limits on power, cooling and space.
AMD is highlighting how its 6th Gen EPYC architecture scales from processor to rack. The company says the processors are designed to turn power, cooling and space constraints into more productive rack-level performance.
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AMD is pitching its 6th Gen EPYC 9006 server processors around a data-center constraint that individual chip benchmarks can miss: operators deploy racks with fixed limits on power, cooling and floor space.
The company’s rack-scale analysis models how much work two-socket systems can fit inside a 100 kW rack. AMD says that approach better reflects deployable capacity because a denser or more efficient processor can let an operator install more nodes without exceeding the same power and thermal envelope.
The 6th Gen family, previously code-named Venice, uses AMD’s Zen 6 architecture and TSMC’s 2 nm process technology. AMD’s EPYC 9006 overview lists up to 256 cores and 512 threads per socket, as many as 16 DDR5 memory channels, MRDIMM speeds up to 12,800 MT/s and PCIe 6 connectivity.
Those specifications matter at rack scale because core density, memory bandwidth and I/O determine how many useful workloads can run within the rack’s shared limits. AMD says liquid-cooled racks built around the current 192-core EPYC 9965 can exceed 27,000 CPU cores, while Venice is architected to scale beyond 36,000 cores in the same class of rack.
AMD estimates that its current EPYC 9965 delivers 2.37 times the normalized rack-level throughput of Nvidia Vera across six proxy workloads. It projects a 3.30-times result for the 256-core Venice configuration. The workload set covers general computing, server-side Java, web serving, key-value storage, in-memory caching and relational databases.
These are not independent production measurements. AMD describes the 100 kW comparison as a modeled scenario and says the Venice and Vera configurations use estimated or projected performance. Actual capacity will depend on system design, software, workload mix and operating conditions. The useful claim is therefore narrower than a universal speed advantage: AMD designed EPYC 9006 to put more CPU resources into a fixed rack budget, and its published model estimates how that density could translate into throughput.
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