This could push annual production past six million NPUs.
I did some lower bound mafs (h/t @jukan05, @zephyr_z9). 950 logic dies are ≤430mm^2, 2 per NPU. TSMC had 0.09 defects/cm^2 in 2019, on 7nm DUV. Assume SMIC is >3x worse still. 30% yield, 20 NPUs/wafer. 600k wafers/year, let's say 50% AI allocation. 6 million NPUs, maybe 6 GW.
Users praised SMIC's potential to yield millions of Huawei Ascend NPUs yearly because it signals strong, capable computing power for the chips.
@teortaxesTex @jukan05 Ur assumptions are wrong Yield for 950 is in the 50%-60% range Kirin is much higher (I have read multiple reports about this and also confirm this with multiple people)
I did some lower bound mafs (h/t @jukan05, @zephyr_z9). 950 logic dies are ≤430mm^2, 2 per NPU. TSMC had 0.09 defects/cm^2 in 2019, on 7nm DUV. Assume SMIC is >3x worse still. 30% yield, 20 NPUs/wafer. 600k wafers/year, let's say 50% AI allocation. 6 million NPUs, maybe 6 GW.
@teortaxesTex @jukan05 @zephyr_z9 why such low yield? btw, I think 6m AI chip this yr is too many, but I also can't see them devoting 25k wpm to NPUs.
Keep in mind that AI chips have similar compute units all over, so you can just disable part of the chip w/ defects.
shh Zephyr. I know there were noises that they reached 40% yield on 910C. This implies defect density of 0.15 and very neatly translates to 54% yield on 950. 34 NPUs/wafer, 10.3M 950-equivalents/year. Remarkably in line with old SemiAnalysis estimate btw.
@teortaxesTex @jukan05 Ur assumptions are wrong Yield for 950 is in the 50%-60% range Kirin is much higher (I have read multiple reports about this and also confirm this with multiple people)
This assumes 50K WPM 7nm at SMIC, no other fabs, and blends in all Chinese AI compute as Huawei-shaped NPUs. None of this is true but I think tradeoffs taken are similar for other vendors. bonus: this defect density gets us ≤20% yield for 910Cs, as rumored in 2024. Lower bound.
I did some lower bound mafs (h/t @jukan05, @zephyr_z9). 950 logic dies are ≤430mm^2, 2 per NPU. TSMC had 0.09 defects/cm^2 in 2019, on 7nm DUV. Assume SMIC is >3x worse still. 30% yield, 20 NPUs/wafer. 600k wafers/year, let's say 50% AI allocation. 6 million NPUs, maybe 6 GW.
@teortaxesTex @jukan05 @zephyr_z9 HH will too, so there are other players coming online. just saying theoretically, they probably can produce 6 million Ascend chips this yr, but what they actually end up producing is a different story.
For DS, even 5 Atlas-950 will be quite the help.
@teortaxesTex @jukan05 @zephyr_z9 HW has to probably split the SMIC capacity w/ Cambricon & others. BD is hesitant to throw their full weight behind Ascend.
BD, Alibaba & probably Baidu & Tencent are getting their chips made outside of Chinese fabs.
There is a question of demand b4 Atlas-950 proves itself
@teortaxesTex @jukan05 *confirmed
@teortaxesTex @jukan05 Ur assumptions are wrong Yield for 950 is in the 50%-60% range Kirin is much higher (I have read multiple reports about this and also confirm this with multiple people)
In short, this does not dissolve the 950 SuperCluster question (524K NPUs would still be a chunk of China's output, and much more of Huawei's allocation), but it's definitely doable, speaking purely of logic dies. …total maybe 10% of US. hawks are BSing.
But seriously. Does anyone believe this? Eric Xu at Huawei Connect 2025 (Sep 18) announced Ascend SuperCluster by Q4'2026. It's a system occupying 64K m^2, with 524K NPUs, tocal 75.5 *Peta*bytes of "HiZQ 2.0" HBM (4 Tb/s). The total BOM is >5x of all CloudMatrix 384's sold.
@tphuang @jukan05 @zephyr_z9 It's the lower bound for their production capacity taking the worst yield rumor, not a prediction of how much they will deploy. Though if anything, I think 25k WPM for this is if anything not enough.
@zephyr_z9 @teortaxesTex @jukan05 Same. Huge redundancy and decent repairability. Should be 50% range.
@teortaxesTex @jukan05 @zephyr_z9 Even for more complex chips like phone SoC, they've managed to raise yield by running @ lower clock speed & disabling certain cores.
N+2 process by this pt is actually quite mature.
@tphuang @jukan05 @zephyr_z9 HW has their own fabs (obfuscated) outside SMIC. BD, afaik, is heavy on Cambricon. Of course it won't be 10M 950DTs uniformly. But again, I don't think other chip designers have accepted much lower yields, so it kind of doesn't matter for total capacity.
@teortaxesTex @jukan05 @zephyr_z9 这个分析思路挺野的，算得挺细
@teortaxesTex @jukan05 @zephyr_z9 这算力，真是够给力
Higher yield changes the logic-die count meaningfully, but my question is whether it matters for realized output. If CXMT is still capped around 2M HBM stacks in 2026, you get the same ~250-300K package ceiling regardless of whether logic yield is 30% or 60%. What's your read on the memory side closing that gap?
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@teortaxesTex @jukan05 @zephyr_z9 SMIC's not as good as TSMC, and everyone knows it. So China's just saying "fine, we'll make it ourselves then."
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@teortaxesTex @jukan05 @zephyr_z9 这算力够干啥的