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    Cerebras Head Shares 3D DRAM Roadmap News from Hot Chips

    Cerebras executive notes D-Matrix and company plans for stacked memory at conference.

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    1 Source, 33d ago, first seen 33d ago

    TLDR

    Sarah Chieng, Head of DevX at Cerebras, posted on X about the Hot Chips conference. She described excitement over DRAM moving into the third dimension and stated that D-Matrix and Cerebras both announced 3D stacked DRAM on their product roadmaps this year. The post adds that for decades one of the fundamental constraints on memory bandwidth has been physical because DRAM and compute live on separate silicon.

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    1 Source, first seen 33d ago

    Combined views

    4.2K

    1 Source, first seen 33d ago

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    6 comments
    55 saves
    11 reposts

    Sentiment

    Positive——Negative

    Summary

    Not enough discussion yet.

    No sentiment analysis available yet.

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    1 Source

    @MilksandMatchaOne of the most exciting themes at Hot Chips this year was watching DRAM move into the third dimension. D-Matrix and Cerebras both announced 3D stacked DRAM on their product roadmaps this year For decades, one of the fundamental constraints on memory bandwidth has been physical: DRAM and compute live on separate silicon, and the interface between them limits how quickly data can move. HBM attacked this problem by stacking DRAM and bringing it closer to compute. 3D integration takes the next step: stack DRAM directly on top of compute. Instead of communicating across the edge of a chip, memory and compute can potentially communicate across its entire surface area. d-Matrix projects this approach can deliver ~3x the bandwidth density of traditional HBM. Making this work at scale is incredibly hard because bonding, power delivery, thermals, yield, testability, packaging, and reliability are all architectural problems. But the direction is important! Because AI is increasingly memory-bound, we need more capacity, but we also need to move that memory closer to compute to access it dramatically faster. The memory hierarchy is being reinvented in real time (!!)

    1 Source

    @MilksandMatchaOne of the most exciting themes at Hot Chips this year was watching DRAM move into the third dimension. D-Matrix and Cerebras both announced 3D stacked DRAM on their product roadmaps this year For decades, one of the fundamental constraints on memory bandwidth has been physical: DRAM and compute live on separate silicon, and the interface between them limits how quickly data can move. HBM attacked this problem by stacking DRAM and bringing it closer to compute. 3D integration takes the next step: stack DRAM directly on top of compute. Instead of communicating across the edge of a chip, memory and compute can potentially communicate across its entire surface area. d-Matrix projects this approach can deliver ~3x the bandwidth density of traditional HBM. Making this work at scale is incredibly hard because bonding, power delivery, thermals, yield, testability, packaging, and reliability are all architectural problems. But the direction is important! Because AI is increasingly memory-bound, we need more capacity, but we also need to move that memory closer to compute to access it dramatically faster. The memory hierarchy is being reinvented in real time (!!)