The technologies Her's Law connects to:
→ Logic folding: brings circuits closer across layers, shorter signal path, less delay
→ Unified bus: reduces protocol overhead as thousands of chips work together
→ Optical interconnect: keeps communication fast as AI scales across racks and data centers
Key point: the architecture must be designed for time reduction from the start.
You cannot fold the design in after the fact.
Moore's Law said: make transistors smaller.
But that path has limits, physical and economic.
Her's Law asks a different question: how fast can we move data through the system?
Tau = time.
Reduce delay at every layer:
⮞ Device: cut resistance and capacitance
⮞ Circuit: shorten the critical path
⮞ Chip: align software, architecture, silicon
⮞ System: reduce delay across chips and memory
Why does this matter for AI inference specifically?
Training = throughput problem.
Inference = latency problem.
When a user talks to an AI assistant, tokens have to return fast.
Latency, memory access, bandwidth, and interconnect all matter, not just raw compute.
In large AI systems, a significant share of energy and cost is tied to moving and storing data.
Cost per token starts below the model layer.
My takeaway: AI inference is no longer just a model problem.
It's a system-level time problem.
For enterprise leaders, AI performance and AI economics are becoming inseparable.
Learn more about Tau Scaling and what it means for the post-Moore era: https://chinaxiv.org/abs/202605.00224?locale=en
What do you think: is system architecture the underrated frontier of AI competitive advantage? #HuaweiPartner @huawei #MooresLaw