Cooling requires stacked SRAM and a microchannel diamond layer
@teortaxesTex W2W HB is easier than D2D or D2W
ok what the hell. I missed this completely So, Huawei expects to deploy LogicFolding Ascends in 2030/31, and have >400 Mtr/mm^2, *and* have single-chip power draw of 30KW. I think this must mean heavy design for yield and, likely, Cerebras-style wafer-scale engines.
@zephyr_z9 Yes, but this is a very ambitious design on its own terms I guess it might not be that hard though. Something like SRAM on the bottom, diamond with microchannels on top, they could cool it.
@teortaxesTex W2W HB is easier than D2D or D2W
Cooling requires stacked SRAM and a microchannel diamond layer
@teortaxesTex W2W HB is easier than D2D or D2W
ok what the hell. I missed this completely So, Huawei expects to deploy LogicFolding Ascends in 2030/31, and have >400 Mtr/mm^2, *and* have single-chip power draw of 30KW. I think this must mean heavy design for yield and, likely, Cerebras-style wafer-scale engines.
@zephyr_z9 Yes, but this is a very ambitious design on its own terms I guess it might not be that hard though. Something like SRAM on the bottom, diamond with microchannels on top, they could cool it.
@teortaxesTex W2W HB is easier than D2D or D2W