Huawei targets a 30 kW wafer-scale processor by 2030.
the crazy part in Tingbo He's paper that I missed is that Ascend isn't going to use LogicFolding until 2030s. They don't have the tools to design their NPUs in 3D. Frankly this looks very bad for them, so bad I think it'll be revised.
ok what the hell. I missed this completely So, Huawei expects to deploy LogicFolding Ascends in 2030/31, and have >400 Mtr/mm^2, *and* have single-chip power draw of 30KW. I think this must mean heavy design for yield and, likely, Cerebras-style wafer-scale engines.
Huawei targets a 30 kW wafer-scale processor by 2030.
the crazy part in Tingbo He's paper that I missed is that Ascend isn't going to use LogicFolding until 2030s. They don't have the tools to design their NPUs in 3D. Frankly this looks very bad for them, so bad I think it'll be revised.
ok what the hell. I missed this completely So, Huawei expects to deploy LogicFolding Ascends in 2030/31, and have >400 Mtr/mm^2, *and* have single-chip power draw of 30KW. I think this must mean heavy design for yield and, likely, Cerebras-style wafer-scale engines.
