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    Sharon Zhou Predicts Flops for Memory Tradeoffs in AI

    AMD AI VP anticipates optimizations driven by shifting hardware costs.

    SZ
    1 Source, 29d ago, first seen 29d ago

    TLDR

    Sharon Zhou, VP of Engineering and AI at AMD and former Lamini CEO, posted that a large wave of algorithms, architecture changes, and performance optimizations will trade more flops for less memory. She linked the expected shift to the dropping relative cost of flops per token compared to HBM per token. Zhou said she is excited to see what gets invented. The post reflects her views drawn from her engineering background at Stanford, Google, and Harvard.

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    10.6K

    1 Source, first seen 29d ago

    Combined views

    10.6K

    1 Source, first seen 29d ago

    157 likes
    157 likes
    9 comments
    39 saves
    9 reposts

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    9 comments
    39 saves
    9 reposts

    Sentiment

    Positive——Negative

    Summary

    Not enough discussion yet.

    No sentiment analysis available yet.

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    1 Source

    @realSharonZhouthere is about to be a large wave of algorithms, architecture changes, and performance optimizations that trade more flops for less memory because the relative cost of flops per token to hbm per token is dropping. excited to see what we invent!

    1 Source

    @realSharonZhouthere is about to be a large wave of algorithms, architecture changes, and performance optimizations that trade more flops for less memory because the relative cost of flops per token to hbm per token is dropping. excited to see what we invent!