CPU core layout reportedly has 14% less total wire and 93% fewer routing violations

A user reports that improvements to a CPU core layout left it with 14% less total wire and 93% fewer routing violations, with more optimizations underway. They say four of its five big blocks are hardened multiplier macros. Darker blue regions help support a feature they expect to be useful for running local models, while the fifth block holds another feature they have not disclosed.