What is Digg?74 Comments
- subxero37, on 10/10/2007, -9/+28I love AMD, but I think they've just been throwing around tons of buzzwords and technobabble lately. Also, their product line is complicated to understand. For example, there is Socket 754, 939, 940 (one more pin?), socket AM2, AM2+, socket F (1207 pins, holy cow) and probably more sockets to come. It's rather confusing. Intel processors seem to be using LGA775, and I haven't seen any others since mPGA 478.
Their new processor core ventures are dubbed various names, all of which are confusing -- it just seems like they're throwing around words to get people to say 'ooh' and 'ahh'. The slated Phenom processor is Barcelona, as far as I know. Beyond that, there's Fusion, which is very vague and given AMD's often-higher thermal envelope, I dunno how shoving GPU-related functions on a die would benefit the situation, especially given how hot GPUs get in their own right. There's also Bobcat, and Bulldozer, both of which are being touted as incredible architectures, when almost no information is known about them, except that it'll let AMD "build a processor" out of "building blocks". I really think they're just throwing random stuff around.
However, with this announcement, it looks like AMD is and will continue to be a serious player in the market, given that the Xbox and the Wii both use ATI/AMD-based GPUs. Also, I think the world shat bricks when AMD introduced x86-64, and then Intel copied AMD, so maybe AMD's on the right track. It's hard to tell, I guess. I'll hope for the best. All but one of my computers are AMD-based. - WiseWeasel, on 10/10/2007, -1/+19Altivec was originally developed by Motorola to target their customers who wanted a DSP chip for embedded uses, things like video encoder/decoders and networking equipment. For those kinds of dedicated high-throughput tasks, it made a lot of sense to dedicate the die space to this co-processing unit. For general-purpose computing, it really didn't come into play very often, and most users rarely took advantage of it. As video encoding/decoding and other vector-intensive tasks have become a bigger part of general purpose computing, it makes sense to build up this capability. These CPU designers only have so many registers and only so much die space to work with to keep the power/performance profile they want, so it's not surprising that such a specialized function hasn't been implemented until now. If this turns out to be a significant advantage for AMD's processors, I'm sure Intel will shortly follow suit; otherwise, it'll fade away. It's ridiculous for end users to be demanding CPU architectural features without knowledge of the cost/benefits of implementing them. While Apple might have been pretty successful at marketing Altivec's abilities and advantages, at the end of the day, Intel and AMD's solutions ended up being at an advantage in price/performance/power requirements for the vast majority of computing tasks.
- geminitojanus, on 10/10/2007, -1/+17MMX was introduced into x86 in 1997 too, you know. It was generally a ***** because it shared registers with the FPU and had all kinds of strange performance properties that were largely solved by SSE and even more so, SSE2. Altivec is a much cleaner implementation of streaming extensions, but then again the PowerPC architecture in general is very smooth and streamlined
- kronix2, on 10/10/2007, -2/+14SSE5 does not include all of the SSE4 instructions. http://bilder.doerpe.net/misc/sse5-and-others.jpg
AMD's SSE5 will compete with Intel's SSE4. IIRC, they have a cross-licensing arrangement which enables them to use the other party's instructions, which makes AMD's decision to branch out and create their own instruction set a confusing one. 3DNow! and its spawn were pretty much useless, so I'm assuming SSE5 will deliver real, quantifiable performance increases.
Prediction: SSE4 support will be implemented by many many more developers, due to low sales of AMD's SSE5 chips in the face of Intel whipping them with their 45nm CPUs. SSE5 will die a slow death unless Intel decides to adopt it.
And please, AMD, get your new CPUs out so Intel actually has some competition. Right now, Core 2 Duos are the only choice unless you want to pay for a painfully inferior product. I want Barcelona to succeed so AMD doesn't tank. If AMD implode, what incentive will Intel have to put out another chip as good as the Core 2 Duo? - DesuKN, on 10/10/2007, -3/+15"Hey guys, we're still relevant!"
"Guys?"
"Oh, I see. You're over there at Intel and their Quintuple-Core CPU/GPU hybrid that also makes toast" - TheGuruStud, on 10/10/2007, -2/+12754 was to get the damn K8 to market (no dual channel, but of course still raped intel), a rush, since it was behind schedule (as everything is these days, especially when you're the company doing the innovating). 939 and 940 are the same thing. 939 - consumer, 940 - server so dumb asses can't claim they don't fit and break something. You don't get a cookie for that one. Again, AM2, AM2+ and AM3, all the same thing except with different number of HTT and PCI-e lanes (supporting a wide range of CPUs and their abilities along with compatibility). Socket F is server, they need the extra pins to handle all of the multi-socket, multi-cpu interaction. You get a chocolate chip for that one.
And what about 775? Oh yeah, it sucks ass. FSB FTW lol. - noisymime, on 10/10/2007, -4/+10SSE3 was the equal or better of Altivec, this description is simply pandering to the Apple zealots who for some reason think a technology that was developed in the 90's, can somehow still be better than the latest and greatest. Altivec was WELL ahead of its time, but that time was 10 years ago. For a full evaluation and performance comparison of these technologies, read http://noisymime.org/blogimages/SIMD.pdf
- Giga, on 10/10/2007, -1/+7Does it do the dishes afterwards? I've always wanted a CPU with everything, including the kitchen sink...
- jhurliman, on 10/10/2007, -0/+6Ahh, now we can write code that detects 3DNow/SSE/SSE2/SSE3/SSE4/SSE5/Altivec at runtime, and write hand-optimized code for each path. The best part is because of cache corruption from frequent context switches that happen with multithreaded code on new dual core processors, simple GCC autovectorization code often runs better then many of those. CPU engineers are innovating a lot quicker than software developers can keep up with nowadays, especially when you have to target four year old machines as your base architecture.
- majortom1981, on 10/10/2007, -2/+7MY question is can somebody tell me what the difference between the SSE4 instructions that Intel just put out and these SSE5 instructions that AMD are putting out? Also how long would it take to get developers to use sse5 when developers really havent used SSE4 yet? ALSO wasnt SSE designed by intel ?
- yabos, on 10/10/2007, -0/+5If you're on OS X you can just use the Accelerate.Framework and let the OS do the decisions of which CPU you are on and which instructions to use. Sure it's probably not quite as efficient as you writing all your own specific code for each different SSE but you will save a ton of time not worrying about it.
- TheGuruStud, on 10/10/2007, -1/+5oops, i meant multi-core instead of multi-cpu since multi-socket takes care of that. More HTT lanes FTW!!! No sarcasm this time haha.
- specialK16, on 10/10/2007, -0/+4"The use of a third operand register can significantly increase performance for some types of codes, especially in hand-tuned code"
That's pretty much it. - dzorz, on 10/10/2007, -2/+6Altivec doesn't support doubles, making it almost useless anywhere where doubles are required. On the other hand even SSE2 processors support doubles.
- SirG3, on 10/10/2007, -0/+4http://wikipedia.org/wiki/SSE5
I've always wanted the PHMINPOSUW instruction... - geminitojanus, on 10/10/2007, -0/+4It means for some specific operations, mostly relevant to signal processing code, things are going to get a lot faster; according to their numbers about 30% faster on DCTs and 5x faster AES.
- OrangeTide, on 10/10/2007, -0/+3AMD is a trademark, so yes you can trademark 3 letter acronyms.
- LordofShadows, on 10/10/2007, -0/+3New assembly instructions that only work on certain processors.
- jhurliman, on 10/10/2007, -1/+4The problem is that compiling code with GCC autovectorization on one platform and running it on thousands (the model of pretty much all software distribution other then Gentoo and the like) won't optimize the code in a manner that is the absolute best for every machine out there. In the Second Life client there is a very heavy choke point that involves a matrix transformation when building avatar meshes, and the solution to optimize it has been writing tons of different code paths and then a small test at runtime that tests each code path that has been compiled in (obviously Altivec is not going to be compiled in on some platforms, and trying to run SSE2 instructions on an old Athlon Thunderbird will cause a crash). Each path is profiled and the fastest one is chosen which sounds great, but the overhead of shipping all these different builds with SSE2 on/off, Altivec on/off, setting up your build scripts to turn all of these flags on and littering #define ENABLE_BLAH all over the code, writing the profiling code etc. is a mess to deal with. Ironically enough the only languages that could truly take advantage here are JITed languages like .NET where the runtime could realize the machine supports SSE5 and compile from CIL to bytecode with that in mind, doing autovectorization to take advantage of 128-bit registers.
- geminitojanus, on 10/10/2007, -0/+3Actually the software guys are pretty much in lockstep with the hardware developers. Software developers have been playing around with DSP-like operations for years now, and that's all these really are. The biggest deal will be getting them into compilers so we don't have to hand tune code, but GCC will likely get these instructions and intrinsics within a couple of weeks (even if it might be months before the autovectorizer can process them).
- SteveMax, on 10/10/2007, -0/+3Checked it. Buried it. Even though the site is interesting, you are spamming it, so the story is spam.
- OrangeTide, on 10/10/2007, -0/+3I think AltiVec was a much cleaner design. But in terms of performance and functionality SSE3 is just as good.
3DNow was actually pretty good too and was out way before any of that SSE stuff. No it didn't do half what AltiVec did, but you could string together a few operations to do some matrices with it. - Abomonog, on 10/10/2007, -1/+4Actually intel fought back with going nuts on dual and quad prossessers. When the X64 version of Unreal Tourney came out and proved to the world that properly written X64 programs could indeed run faster than their X86 counterparts (A LOT faster) intel tried the X64 platform and got nailed for copying the AMD chips. So intel went nuts with with the multi-core CPU thing. Kind of sad. Even though the courts were upholding the law properly when intel got busted the X64 platform pretty much got crushed. I've got an X64 CPU and there's no sense in supporting it because the ONLY program out there that makes full and proper use of it is the X64 version of UT. :(
- geminitojanus, on 10/10/2007, -0/+3Similar librray, only cross platform (builds anywhere via GCC) and BSD licensed: http://liboil.freedesktop.org/wiki/
It doesn't have nearly as many optimized operations, but the few that are there will cover quite a few use cases. - Elranzer, on 10/10/2007, -0/+3"AMD" is not an acronym. It's an initialism.
- msgyrd, on 10/10/2007, -0/+3If you don't know from the article, there's no concise way to explain it other than:
Your computer will be faster without the Ghz increasing. - Giga, on 10/10/2007, -1/+3Cause I can't be bothered. Why should I?
- etnu, on 10/10/2007, -1/+3Very few software developers are ever going to even think about how to take advantage of any of the extensions, and most of those are just going to set the march flag and be done with it. Some games or specific applications with a huge performance bottleneck might do this too, but in general nobody actually worries about machine instructions. Hell, most developers aren't even using languages / platforms that give you control over how instructions are used anyway.
- TheGuruStud, on 10/10/2007, -0/+2show some love for slot A too :P
- ratsg, on 10/10/2007, -0/+2Sparc is one of the CPU's that Sun uses. Lots of companies use the Sparc processor. Sparc is not a "Sun only" cpu.
http://www.sparc.org/ - fuzzynyanko, on 10/10/2007, -1/+3Ballsy, yet complicated. Hopefully Intel and AMD will cross-license SSE4 and SSE5. I'm surprised they went with the SSE name instead of making a new name.
- Elranzer, on 10/10/2007, -2/+4Odd that they're calling it SSE5, since Intel developed SSE through SSE4. I wonder if one can or can't trademark a three-letter initialism like SSE.
- jhurliman, on 10/10/2007, -0/+2RE: liboil, yes it is a very cool lib and Second Life is in the process of switching over to use that. I suppose things aren't so bad (from an implementation standpoint) if they are abstracted away in a lib like that, and hopefully some of the SL devs can contribute back to it as well.
- zeras, on 10/10/2007, -0/+2Good move AMD good move :-)
- inactive, on 10/10/2007, -0/+2Well, Intel were unable to trademark/copyright the name 586 (hence replacing it with 'Pentium'), so it would seem reasonable that they can't do the same with 'SSE' either.
- LordofShadows, on 10/10/2007, -0/+2There is a diagram in a forum linked in the article, developers can take advantage of this the second they get the hardware to test the code on, (I guess they could use the spec, but that would be odd) developers wont really use this more than sse4. After the whole mmx/sse thing I believe extensions were opened for anyone to implement on their x86 cores. Via has cpu's with sse extensions as well.
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http://games.qlbe.com/game25/25 - OrangeTide, on 10/10/2007, -0/+2I never use doubles in games. Many 3D model formats and game protocols even use singles still. Do you use doubles?
- OrangeTide, on 10/10/2007, -0/+2I remember when your choices were SuperSocket7 from AMD, and socket7, socket8 and slot1 from intel. (plus those overdrive sockets with extra pins around the edge)
- OrangeTide, on 10/10/2007, -0/+2I'm still waiting for AMD or Intel to adopt VIA Padlock on their chips. REPZ XCRYPT-CBC ftw!
- Nexusmonkey, on 10/10/2007, -0/+2In english this article means... what?
- incd, on 04/18/2008, -2/+3So. What does this really mean to us?
- geminitojanus, on 10/10/2007, -2/+3There's actually a library floating around to solve this very problem: LibOIL (Library of Optimized Inner Loops). At startup it automatically profiles the processor and chooses the right codepaths, and all you have to do is use the provided API and you'll know you'll be taking the best codepath. Sounds like Second Life needs to get its act together and use it.
- kronix2, on 10/10/2007, -2/+3I sure as hell hope that was sarcasm.
- LordofShadows, on 10/10/2007, -1/+2There is a new set of assembly code instructions that no one will really use in their software.
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http://www.kholla.com - mhmdkhamis, on 12/14/2007, -0/+1MY question is can somebody tell me what the difference between the SSE4 instructions that Intel just put out and these SSE5 instructions that AMD are putting out? Also how long would it take to get developers to use sse5 when developers really havent used SSE4 yet? ALSO wasnt SSE designed by
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http://www.paramegsoft.com/forum/ - wallker, on 09/12/2008, -0/+1Thank You
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http://www.afif.ws/news - Konstantinopol, on 10/10/2007, -0/+1Does it do the dishes afterwards? I've always wanted a CPU with everything, including the kitchen sink...
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